One chip solution for ATM Network Interface Card (NIC)

Internal SDH STM-1 Framer

External UTOPIA interface for other PHYs : 25 Mb/s UTP, 100 Mb/s TAXI etc.

Built-in Clock Recovery (155.520 MHz)

Supports maximum 65,536 ATM virtual connection

AAL5 SAR Function(CRC-32 included)

Supports for AAL3/4, AAL0

Traffic Scheduling for CBR, VBR, UBR using schedule table

cell insertion and extraction for OAM, RM (CRC-10 included)

Built-in loop-back test

PCI Bus Master, Slave interface : Rev 2.1

Supports for Ring based Multi-access : Cell Copying, Relaying & Add/Drop

Minimal QOS,Traffic Parameter change for a VC afflicted by Add/Relay

Package : 304PQFPt ( 0.5 u LSI Logic LCB500K Standard Cell Technology )

Die Size : 11.5 mm x 11.5 mm ( approx. 250,000 Gates)